Microprocessor architecture capable of supporting

专利名称：Microprocessor architecture capable of

supporting multiple heterogenousprocessors

发明人：Lentz, Derek J.,Hagiwara, Yasuaki,Tang,

Cheng-Long,Lau, Te-Li

申请号：EP97119364.4申请日：19920707公开号：EP0834816A2公开日：19980408

专利附图：

摘要：A computer system comprising a microprocessor architecture capable ofsupporting multiple processors comprising a memory array unit (MAU), an MAU systembus comprising data, address and control signal buses, an I/O bus comprising data,address and control signal buses, a plurality of I/O devices and a plurality of

microprocessors. Data transfers between data and instruction caches and I/O devices anda memory and other I/O devices are handled using a switch network port data andinstruction cache and I/O interface circuits. Access to the memory buses is controlled byarbitration circuits which utilize fixed and dynamic priority schemes. A test and set bypasscircuit is provided for preventing a loss of memory bandwidth due to spin-locking. Acontent addressable memory (CAM) is used to store the address of the semaphore andis checked by devices attempting to access the memory to determine whether thememory is available before an address is placed on the memory bus. Writing to theregion protected by the semaphore clears the semaphore and the CAM. A row matchcomparison circuit is provided for reducing memory latency by giving an increasedpriority to successive requests for access to memory locations having the same rowaddress. Dynamic switch/port arbitration is provided by changing the priority of thedevices based on the intrinsic priority of the device, the number of times that a requesthas been serviced based on a row match, the number of times that a device has beendenied service and the number of times that a device has been serviced. Circuits are alsoprovided for invalidation and intervention such that master and slave devices areoperating with the most current information. Circuits are also included to provide

dynamic memory refresh on an automatic basis by signals from any one of the processorssince each of the processors keep track when a memory refresh has occurred and thelapse time between refresh requests.

申请人：SEIKO EPSON CORPORATION

地址：4-1, Nishi-shinjuku 2-chome, Shinjuku-ku Tokyo 163 JP

国籍：JP

代理机构：Grünecker, Kinkeldey, Stockmair & Schwanhäusser Anwaltssozietät

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