Integrated Device Technology, Inc.APPLICATION
NOTEAN-155
By Anupama Hegde
INTRODUCTION
Phase-locked loops(PLLs) are used extensively in theareas of analog system design and communication systems.With the increasingly stringent timing constraints in highperformance systems today, phase-locked loops are beingintroduced in more general digital designs as well. The com-puter motherboard is one example of such a mainstreamapplication.
The key advantages that PLLs bring to clock distributionapplications are phase/delay compensation, frequency multi-plication and duty-cycle correction. This application noteintroduces users to PLL operation and gives guidelines ontheir use and application.
IDT makes several PLL-based clock drivers :
•FCT88915TT - 8 outputs with external loop filter capaci-tor, 3-state outputs and TTL output voltage swings•FCT388915T - 3.3V version of the 88915TT
•FCT3932 - 3.3V programmable PLL with 18 outputs
Most of the discussion below is geared towards IDT’s PLL-based clock chips. The reader is advised to refer to individualdatasheets for specific device characteristics.
TABLE OF CONTENTS
INTRODUCTION..............................................................48TABLE OF CONTENTS...................................................48PHASE-LOCKED LOOP OPERATION............................48Charge Pump................................................................49Loop Filter.....................................................................49VCO..............................................................................50LOOP ANALYSIS.............................................................50ACHIEVING LOCK...........................................................51DELAY COMPENSATION...............................................51
PHASE/FREQUENCYDETECTORREFERENCECHARGE PUMPFREQUENCY MULTIPLICATION.................................51JITTER..........................................................................52SUMMARY....................................................................53REFERENCES..............................................................53
PHASE-LOCKED LOOP OPERATION
A phase-locked loop is a closed loop system with negativefeedback. As the name implies, the output signal “locks” ontoan incoming reference signal. Figure 1 is a simplified blockdiagram showing the main components of a phase-lockedloop.
A PLL typically consists of 4 main components - the phase-frequency detector(PFD), the charge pump, the loop filter andthe voltage-controlled oscillator(VCO). The phase-frequencydetector(PFD) compares feedback and reference signals andgenerates an error signal which is proportional to the magni-tude of the phase/frequency difference between them. Thiserror signal is fed to the charge pump. The charge pumpcurrent controls the magnitude of charge stored in the loopfilter thus converting the PFD output to a control voltage inputrecognizable by the voltage controlled oscillator(VCO). TheVCO generates an output frequency proportional to thiscontrol voltage. The output frequency may be further divideddown before being fed back to the PFD, as shown in Figure 1. When the PLL is “locked”, there is a constant phasedifference (usually zero) between the feedback and referencesignals and their frequencies are matched.
Kd =Ip2πF(s)KosLOOP FILTERVOLTAGE CONTROLLEDOSCILLATORFEEDBACKndiv-by-nFigure 1. Phase-Lock Loop
PHASE-FREQUENCY DETECTOR
The IDT logo is a registered trademark of Integrated Device Technology, Inc.©1996 Integrated Device Technology, Inc.
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PHASE-LOCKED LOOP CLOCK GENERATORSAPPLICATION NOTE AN-155
The function of the Phase and Frequency Detector is togenerate an output signal proportional to the phase/frequencydifference between the reference and feedback signals. Fig-ure 2 shows an example of a PFD implementation. Here theoutput signal takes the form of UP or DOWN pulses which inturn activate the charge pump switch.
Frequency detection capability shortens LOCK time. Com-binatorial PDs do not have frequency detection capability.This phase-only detect is required in datacom where thereference signal is not periodic.
CHARGE PUMP
The charge pump is analogous to a 3-pole switch. It hasonly 3 allowable states : UP, DOWN and OFF. When the FBleads REF, the VCO has to slow down, therefore DOWN isactivated and current IDOWN flows in one direction. When itlags, the VCO has to speed up hence UP is activated andcurrent IUP flows in the other direction. When the PLL is locked,PFD output is in 3-state condition and no current flows.
The purpose of this circuit is to deliver a constant pumpcurrent, Ip, to the loop filter. The duration of the switch ON timecontrols the amount of charge stored in the loop filter, andconsequently the VCO control voltage. The combined transferfunction or gain of the PFD and charge pump is given by , Kd = Ip/2π
VccCLRDREF
QQUP
DFB
CLRQQDOWNIpp\"UP\" switchpositionRFigure 2. Phase Frequency Detector
The UP signal is asserted on every REF clock rising edgeand cleared when both UP and DOWN are high. The DOWNsignal is asserted on every FB clock rising edge and alsocleared when both UP & DOWN are high. If the feedback isfound to lag the reference signal, the output frequency isincreased. When the feedback leads the reference signal, theoutput frequency is decreased. Thus any adjustment of outputphase or frequency is made by adjusting the VCO frequency.Phase error may cause the frequency to overshoot and/orundershoot around the input frequency until a steady-stateoperating point is reached, where both phase and frequencyare matched.
tP = | θe / ωi |where
tP = Duration of UP or DOWN pulse
θe = Phase error between REF and FB signals ωi = Frequency of REF signal
Ip\"DOWN\" switchpositionCFigure 4. Charge Pump & Loop Filter configuration
REFFBUPDOWN(a) REF leads FB(b) FB leads REFLOOP FILTER
The function of the loop filter is to convert the output of thecharge pump to the VCO control voltage and also to filter outany high frequency noise introduced by the PFD. An active orpassive loop filter may be employed. IDT PLLs typicallyemploy a 2nd order passive RC network for the loop filterimplementation. Some PLLs, require external loop filter com-ponents while others integrate all components on the chipitself. The IDT FCT88915TT and FCT3888915T, require asingle external capacitor to be connected externally and theIDT FCT3932, FCT3907 and FCT3908 use internal filters.Normal parametric variations have small effect on the PLL dueto the large internal loop filter resistance typically used.
One of the simplest passive loop filter configurationsconsists of a single resistor and capacitor as shown in Figure4. This constitutes a 1st order filter. A simple 1st order filter issufficient to ensure that transient disturbances do not affectoperation, but designers often use an additional high fre-quency pole to filter out ripple noise. The transfer function ofthe 1st order loop filter takes the form,
F(s) = [ 1/sc ] / [ R + 1/sC ]
Figure 3. PFD operation
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PHASE-LOCKED LOOP CLOCK GENERATORSAPPLICATION NOTE AN-155
= 1 / [1 + sRC]
2nd order filters are also commonly used in PLLs becauseof their good stability characteristics.The 2nd order loop filtertransfer function takes the form,
F(s) = [ R2 + 1/sC ] / [ R1 + R2 + 1/sC ] = [ 1 + sR2C ] / [ 1 + s( R1 + R2 )C ]
A 3rd order filter may be employed but tends to increasethe chances of instability.
VCO
The VCO is typically a simple multivibrator (schmitt trigger)or an n-stage current-starved inverter ring. A VCO introducesan additional pole at the origin since its output phase is anintegral of frequency over time. The VCO gain or transferfunction is given by
Kv = Ko/s.
The VCO output may be divided down to obtain the re-quired output frequency. This ensures better clock resolutionand also increases the loop gain which is desirable as will beshown later.
VCO design considerations include - linearity, operatingfrequency range, duty-cycle, gain and noise performance. Alinear transfer function is desirable since it makes overall PLLperformance more predictable. VCO linearity should accommo-date process, temperature and Vcc variations.
LOOP ANALYSIS
The frequency domain is commonly used in the analysis ofPLLs as a matter of convenience and simplicity. Although aPLL is generally composed of both linear and non-linearelements, the Laplace transform is widely used for determin-ing loop stability and frequency response characteristics.Justification for this is found in [1] and [2]. Figure 1 shows asimple linear feedback system, where the open loop andclosed loop transfer functions are given by,
Open Loop Transfer Function = θo / θe = G(s).H(s)Closed Loop Transfer Function = θo / θi
= G(s) / [ 1+ G(s).H(s) ]The corresponding transfer functions for a PLL, also shownin Figure 1, are given by,G(s) = Kd. F(s). KoH(s) = n
Thus,
PLL Open Loop Transfer Function = θo / θe
= Kd. F(s). Ko. n= n. Ko.Ip.F(s) / 2πs
PLL Closed Loop Transfer Function = θo / θi
= Kd. F(s). Ko / [ 1+ Kd. F(s). Ko. n ]= Ko.Ip.F(s) / [2πs + n. Ko.Ip.F(s)]
Ideally, PLL output is required to follow the PLL inputclosely. From the above equation, this is possible if G(s) isinfinite and H(s) is finite and non-zero. Infinite gain beingimposible, a high loop gain is desirable. In addition, the loopis required to reject noise and also maintain stability in the
range of interest. In order to reject noise, the loop should haveappropriate cut-off or bandpass characteristics.
Absolute and relative stability of the loop can be deter-mined by a number of popular graphical and analytical tech-niques such as the Root Locus method, Nyquist plots, Bodeplots and the Routh-Hurwitz criterion.
Root-Locus
Here the locus of the roots of H(s)G(s) or the open looptransfer function is sketched with the loop gain, K, varying fromzero to infinity.
For stability, all poles must lie in the left half plane. Therelative positions of the poles and zeroes of H(s)G(s) deter-mine the relative stability of the loop.
Imaginary AxisK-->Real AxisK = 0s = -aK = 0s = 0K-->Figure 5. Example of Root-Locus plot
For example if H(s)G(s) = A / [s (s+a)], 2 poles exist at s=0and s=-a and zeroes at plus and minus infinity. Thus the rootlocus moves from the poles to the zeroes as shown in Figure5.
Nyquist plot
The Nyquist plot is a plot of the open loop transfer functionG(s)H(s), with s varying from zero to infinity.
The Nyquist stability criterion states that a system is stableif the Nyquist plot encircles the (-1, j0) point as many times asthe number of poles of G(s)H(s) that are in the right half of thes-plane and the encirclements, if any should be in the clock-wise direction.
Bode plot
This technique involves plotting the magnitude and phaseof the closed loop transfer function over frequency as shownin Figure 6. The loop is unstable if the gain magnitude isgreater than zero for values of phase below -π.
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PHASE-LOCKED LOOP CLOCK GENERATORSAPPLICATION NOTE AN-155
DELAY COMPENSATION
M(ω)ωωφ(ω)mFigure 6. Example of Bode magnitude and phase plots
Routh-Hurwitz
This analytical technique uses the roots of the characteris-tics equation - 1 + G(s)H(s) to determine absolute stability.
Typically any delay through the PLL itself is compensatedout because a PLL phase shifts the output so that the phasedifference between FEEDBACK and REFERENCE is nomore than the tPD limit. In the locked state, the PLL has aconstant static phase error which is referred to as the tPD orpropagation delay of the PLL. In most cases this static phaseerror is quite small and PLLs are treated as “zero-delay”devices. The static phase error limit of the PLL is representedby the propagation delay or tPD specified in datasheets.
A mismatch in the paths from the output to the receivingdevice input and from the output to the feedback input mayalso cause some phase shifting of the output signal relative tothe PLL REFERENCE input. Any downstream delay in theoutput path can be compensated out by matching the outputand feedback path delays. Figure 7 shows a few examples ofsuch delay compensation using a PLL.
FREQUENCY MULTIPLICATION
Divisors in the feedback loop cause the REFERENCE tobe multiplied up, as long as the stepped up output frequencyis within the operating frequency range of the PLL. The tablein Figure 8 illustrates how the value of the divisor in thefeedback path affects the PLL output frequency.
ACHIEVING LOCK
If the FEEDBACK signal follows (once the phase error fallswithin the specified tPD LOCK-in range a n-bit counter isactivated) the REFERENCE signal for n consecutive cycles,the “LOCK” output is asserted. In this condition, FEEDBACKis within tPD nasoseconds of REFERENCE. If the phase errorwanders outside this range, the counter is reset and the“LOCK” signal is deasserted.
REFERENCE TO REGISTER CLK - \"ZERO DELAY\"Path A = 1nsFEEDBACKREFERENCEPLLREFERENCEREFERENCECLKPath B = 1nsREGISTERCLKOUTPUT(a) Path A Delay = Path B DelayZero delayREFERENCE TO REGISTER CLK - PHASE ADVANCEPath A = 1nsFEEDBACKREFERENCEPLLPath B = 0.5nsREGISTERCLKREFERENCEREFERENCECLKtD = Path B - Path A = (0.5 - 1.0)ns = -0.5ns(b) Path A Delay > Path B DelayREFERENCE TO REGISTER CLK - PHASE DELAYPath A = 0.8nsFEEDBACKREFERENCEPath B = 1.2nsPLLREGISTERCLKREFERENCEREFERENCECLKtD = Path B - Path A = (1.2-0.8)ns = 0.4ns(c) Path A Delay < Path B DelayFigure 7. Delay Compensation using PLLs
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PHASE-LOCKED LOOP CLOCK GENERATORSAPPLICATION NOTE AN-155
REFERENCEFEED-BACKPLLVCO÷2÷4O1 (1x)O2 (÷2)O3 (÷4)O4 (÷8)(a)(b)(c)(d)÷8Possible Feedback ConfigurationsThe VCO output is often divided down to different outputsMAX fREF = fMAX(1/n)where,
1/n = Prescale factor in the feedback loop
If Reference frequency = f,FeedbackFeedbackConfigurationfrom
(a)(b)(c)(d)
O1O2O3O4
Output frequencyO1O2O3f2f4f8f
f/2f2f4f
f/4f/2f2f
O4f/8f/4f/2f
Figure 8. Using PLLs to step up/down frequency
JITTER
Jitter is a measure of short term frequency stability. It is the
deviation of the signal edge from its expected position whenthe PLL is locked. System noise is a key factor contributing tojitter so standard guidelines on reducing switching and powerline noise should be observed to reduce output jitter.
Peak jitter parameters measure the difference betweenthe clock period of the signal on a particular cycle and the idealclock period. Peak or absolute jitter is sometimes referred toas phase jitter.
Cycle-to-cycle jitter refers to the difference in clock periodof the signal from one cycle to the next cycle. Cycle-to-cyclejitter is also known as period jitter.
In both cases many such measurements can be taken andstandard deviation and mean values can be computed. Theimportant thing is that the sample rate be no slower than halfthe sampled signal frequency.
Setup and hold time failures in a system are primarilycaused by differences in the clock period from one cycle to thenext rather than the difference between real and ideal clockperiods. Consider the synchronous pipeline in Figure 10. Thecycle-to-cycle jitter could cause a hold (or setup ) time viola-tion. Except for very large magnitudes of jitter, the differencebetween the actual and ideal clock output does not affectsystem operation because no signal is referenced to orclocked on the “ideal” clock edge. For this reason, peak jitteris not as relevant a parameter in real applications as is cycle-to-cycle jitter.
Time interval analyzers or counters and spectrum analyz-ers are used for measuring the various jitter parameters. Highresolution scopes are also able to graphically depict peakjitter. Instrumentation with a high enough sample rate, goodresolution (under 100ps) and sufficient memory should beused for jitter measurements on high frequency clocks.
There are various methods of viewing or representing jitter(both peak and cycle-to-cycle) in both time and frequencydomains. Some of these are histograms, stripcharts, andsimple peak or standard deviation measurements with nographical display of data.
IDEAL CLOCK OUTPUT+∆Θ1+∆Θ2+∆Θ3+∆Θ4+∆Θ5+∆Θ6JITTERED CLOCK OUTPUTPEAK JITTER FUNCTIONCYCLE-TO-CYCLEJITTER FUNCTIONFigure 9. Output jitter
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PHASE-LOCKED LOOP CLOCK GENERATORSAPPLICATION NOTE AN-155
DDEVICEA CLKYDEVICEB CLKSUMMARY
This application note seeks to familiarize the reader withPLL operation and terminology. Some background on thefundamental components of a phase-locked loop and a corre-lation to general control system theory is provided in order togive designers some insight into loop behavior.
REFPLLREFERENCES
[1]“Charge-Pump Phase-lock Loops”, F.Gardner. IEEETransactions of Communications, Vol. Com-28, No.11.
peak Ideal ClockNov 1980.jitterOutput[2] “Phaselock Techniques”, F. Gardner. WileyInterscience. 1979.t2Actual Clockt1[3]“Designing on-chip Clock Generators”, Dao-Long Chen.Outputcycle-to-cycle jitterIEEE Circuits and Devices, July 1992.= t1 - t2[4]“Phase-Locked Loop Circuit Design”, Dan H. Wolaver.
YPrentice-Hall. 1991.
[5]”Phase-Locked Loop Design Fundamentals”, Motorola
reduced hold timeHigh Performance Frequency Control Products hand-due to cycle-to-cycle book.jitter[6]“Automatic Control Systems”, B. Kuo. Prentice-Hall,1985.
[7]“Distortion and Tolerance Mechanisms in High-SpeedFigure 10 Peak vs Cycle-to-cycle jitter
Clock Delivery”, Michael K. Williams, HP High SpeedDigital Symposium 1993.
Input clock53
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