DS90C365

DS90C385/DS90C365

+3.3VProgrammableLVDSTransmitter24-BitFlatPanelDisplay(FPD)Link-85MHz,+3.3VProgrammableLVDSTransmitter18-BitFlatPanelDisplay(FPD)Link-85MHz

GeneralDescription

TheDS90C385transmitterconverts28bitsofLVCMOS/LVTTLdataintofourLVDS(LowVoltageDifferentialSignal-ing)datastreams.Aphase-lockedtransmitclockistransmit-tedinparallelwiththedatastreamsoverafifthLVDSlink.Everycycleofthetransmitclock28bitsofinputdataaresampledandtransmitted.Atatransmitclockfrequencyof85MHz,24bitsofRGBdataand3bitsofLCDtimingandcontroldata(FPLINE,FPFRAME,DRDY)aretransmittedatarateof595MbpsperLVDSdatachannel.Usinga85MHzclock,thedatathroughputis297.5Mbytes/sec.Alsoavail-ableistheDS90C365thatconverts21bitsofLVCMOS/LVTTLdataintothreeLVDS(LowVoltageDifferentialSig-naling)datastreams.BothtransmitterscanbeprogrammedforRisingedgestrobeorFallingedgestrobethroughadedicatedpin.ARisingedgeorFallingedgestrobetransmit-terwillinteroperatewithaFallingedgestrobeReceiver(DS90CF386/DS90CF366)withoutanytranslationlogic.TheDS90C385isalsoofferedina64ball,0.8mmfinepitchballgridarray(FBGA)packagewhichprovidesa44%reductioninPCBfootprintcomparedtotheTSSOPpackage.

ThischipsetisanidealmeanstosolveEMIandcablesizeproblemsassociatedwithwide,high-speedTTLinterfaces.

Features

n20to85MHzshiftclocksupport

nBest–in–ClassSet&HoldTimesonTxINPUTsnTxpowerconsumption<130mW(typ)@85MHzGrayscale

nTxPower-downmode<200µW(max)

nSupportsVGA,SVGA,XGAandDualPixelSXGA.nNarrowbusreducescablesizeandcostnUpto2.38Gbpsthroughput

nUpto297.5Megabytes/secbandwidth

n345mV(typ)swingLVDSdevicesforlowEMInPLLrequiresnoexternalcomponents

nCompatiblewithTIA/EIA-644LVDSstandardnLowprofile56-leador48-leadTSSOPpackage

nDS90C385alsoavailableina64ball,0.8mmfinepitchballgridarray(FBGA)package

BlockDiagrams

DS90C385

©2002NationalSemiconductorCorporationDS100868www.national.com

DS90C385/DS90C365AbsoluteMaximumRatings

(Note1)DS90C385SLCPackageDerating:DS90C385MTDPackageDerating:DS90C365MTDDS90C385SLCESDRating

(HBM,1.5kΩ,100pF)(EIAJ,0Ω,200pF)LatchUpTolerance@25˚C

2.0W

12.5mW/˚Cabove+25˚C16mW/˚Cabove+25˚C10.2mW/˚Cabove+25˚C

IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheNationalSemiconductorSalesOffice/Distributorsforavailabilityandspecifications.SupplyVoltage(VCC)CMOS/TTLInputVoltageLVDSDriverOutputVoltageLVDSOutputShortCircuitDuration

JunctionTemperatureStorageTemperatureLeadTemperature(Soldering,4sec)SolderreflowTemperature(20secforFBGA)MTD56(TSSOP)Package:DS90C385MTDMTD48(TSSOP)Package:DS90C365MTDSLC64(FBGA)Package:

+220˚C

MaximumPackagePowerDissipationCapacity@25˚C

1.63W1.98W−0.3Vto+4V

−0.5Vto(VCC+0.3V)−0.3Vto(VCC+0.3V)

Continuous

+150˚C

−65˚Cto+150˚C

+260˚C

>7kV>500V>±300mA

RecommendedOperatingConditions

MinNomMaxUnits

SupplyVoltage(VCC)OperatingFreeAirTemperature(TA)SupplyNoiseVoltage(VCC)TxCLKINfrequency

20

−10+25+70

85

˚CMHz100mVPP3.0

3.3

3.6

V

ElectricalCharacteristics

Overrecommendedoperatingsupplyandtemperaturerangesunlessotherwisespecified.SymbolVIHVILVCLIINParameter

HighLevelInputVoltageLowLevelInputVoltageInputClampVoltageInputCurrent

ICL=−18mA

VIN=0.4V,2.5VorVCCVIN=GND

LVDSDCSPECIFICATIONSVOD∆VODVOS∆VOSIOSIOZDifferentialOutputVoltageChangeinVODbetweencomplimentaryoutputstatesOffsetVoltage(Note4)ChangeinVOSbetweencomplimentaryoutputstatesOutputShortCircuitCurrentOutputTRI-STATE®Current

VOUT=0V,RL=100ΩPowerDown=0V,VOUT=0VorVCCRL=100Ω,CL=5pF,

WorstCasePattern(Figures1,4)RL=100Ω,CL=5pF,

16GrayscalePattern(Figures2,4)

f=32.5MHzf=40MHzf=65MHzf=85MHzf=32.5MHzf=40MHzf=65MHzf=85MHz

−3.5

1.125

1.25

RL=100Ω

250

345

450351.37535−5

mVmVVmVmAµA

−10

Conditions

Min2.0GND

−0.79+1.80Typ

MaxVCC0.8−1.5+10

UnitsVVVµAµA

LVCMOS/LVTTLDCSPECIFICATIONS

±1±10

TRANSMITTERSUPPLYCURRENTICCTW

TransmitterSupplyCurrentWorstCaseDS90C385

TransmitterSupplyCurrent16GrayscaleDS90C385

3132374229303539

4550556038404550

mAmAmAmAmAmAmAmA

ICCTG

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DS90C385/DS90C365ElectricalCharacteristics

SymbolICCTW

Parameter

TransmitterSupplyCurrentWorstCaseDS90C365

TransmitterSupplyCurrent16GrayscaleDS90C365

TransmitterSupplyCurrentPowerDown

TRANSMITTERSUPPLYCURRENT

(Continued)

Overrecommendedoperatingsupplyandtemperaturerangesunlessotherwisespecified.

Conditions

RL=100Ω,CL=5pF,

WorstCasePattern(Figures1,4)RL=100Ω,CL=5pF,

16GrayscalePattern(Figures3,4)

f=32.5MHzf=40MHzf=65MHzf=85MHzf=32.5MHzf=40MHzf=65MHzf=85MHz

Min

Typ282934392627323610

Max424752573537424755

UnitsmAmAmAmAmAmAmAmAµA

ICCTG

ICCTZ

PowerDown=Low

DriverOutputsinTRI-STATEunderPowerDownMode

Note1:“AbsoluteMaximumRatings”arethosevaluesbeyondwhichthesafetyofthedevicecannotbeguaranteed.Theyarenotmeanttoimplythatthedeviceshouldbeoperatedattheselimits.Thetablesof“ElectricalCharacteristics”specifyconditionsfordeviceoperation.Note2:TypicalvaluesaregivenforVCC=3.3VandTA=+25C.

Note3:Currentintodevicepinsisdefinedaspositive.Currentoutofdevicepinsisdefinedasnegative.Voltagesarereferencedtogroundunlessotherwisespecified(exceptVODand∆VOD).Note4:VOSpreviouslyreferredasVCM.

RecommendedTransmitterInputCharacteristics

OverrecommendedoperatingsupplyandtemperaturerangesunlessotherwisespecifiedSymbolTCITTCIPTCIHTCILTXIT

TxCLKINTransitionTime(Figure6)TxCLKINPeriod(Figure7)TxCLKINHighTime(Figure7)TxCLKINLowTime(Figure7)TxINTransitionTime

Parameter

Min1.011.760.35T0.35T1.5

T0.5T0.5TTyp

Max6.0500.65T0.65T6.0

Unitsnsnsnsnsns

TransmitterSwitchingCharacteristics

OverrecommendedoperatingsupplyandtemperaturerangesunlessotherwisespecifiedSymbolLLHTLHLTTPPos0TPPos1TPPos2TPPos3TPPos4TPPos5TPPos6TPPos0TPPos1TPPos2TPPos3TPPos4TPPos5TPPos6

Parameter

LVDSLow-to-HighTransitionTime(Figure5)LVDSHigh-to-LowTransitionTime(Figure5)

TransmitterOutputPulsePositionforBit0(Figures13,14)(Note5)

TransmitterOutputPulsePositionforBit1TransmitterOutputPulsePositionforBit2TransmitterOutputPulsePositionforBit3TransmitterOutputPulsePositionforBit4TransmitterOutputPulsePositionforBit5TransmitterOutputPulsePositionforBit6

TransmitterOutputPulsePositionforBit0(Figures13,14)(Note5)

TransmitterOutputPulsePositionforBit1TransmitterOutputPulsePositionforBit2TransmitterOutputPulsePositionforBit3TransmitterOutputPulsePositionforBit4TransmitterOutputPulsePositionforBit5TransmitterOutputPulsePositionforBit6

f=65MHzf=40MHz

−0.253.326.8910.4614.0417.6121.18−0.202.004.206.398.5910.7912.99Min

Typ0.750.7503.577.1410.7114.2917.8621.4302.204.406.598.7910.9913.19

Max1.51.50.253.827.3910.9614.5418.1121.680.202.404.606.798.9911.1913.39

Unitsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsns

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DS90C385/DS90C365TransmitterSwitchingCharacteristics

SymbolTPPos0TPPos1TPPos2TPPos3TPPos4TPPos5TPPos6TSTCTHTCTCCD

Parameter

(Continued)

Overrecommendedoperatingsupplyandtemperaturerangesunlessotherwisespecified

Min

f=85MHz

−0.201.483.164.846.528.209.882.50

TA=25˚C,VCC=3.3V

f=85MHzf=65MHzf=40MHz

3.82.8

110210350

6.37.115023037010100

Typ01.683.365.046.728.4010.08

Max0.201.883.565.246.928.6010.28

Unitsnsnsnsnsnsnsnsnsnsnsnspspspsmsns

TransmitterOutputPulsePositionforBit0(Figures13,14)(Note5)

TransmitterOutputPulsePositionforBit1TransmitterOutputPulsePositionforBit2TransmitterOutputPulsePositionforBit3TransmitterOutputPulsePositionforBit4TransmitterOutputPulsePositionforBit5TransmitterOutputPulsePositionforBit6TxINSetuptoTxCLKIN(Figure7)TxINHoldtoTxCLKIN(Figure7)TxCLKINtoTxCLKOUTDelay(Figure8)TxCLKINtoTxCLKOUTDelay(Figure8)

TJCCTransmitterJitterCycle-to-Cycle(Figures15,16)(Note6)

TPLLSTPDD

TransmitterPhaseLockLoopSet(Figure9)TransmitterPowerDownDelay(Figure12)

Note5:TheMinimumandMaximumLimitsarebasedonstatisticalanalysisofthedeviceperformanceoverprocess,voltage,andtemperatureranges.ThisparameterisfunctionalitytestedonlyonAutomaticTestEquipment(ATE).

Note6:Thelimitsarebasedonbenchcharacterizationofthedevice’sjitterresponseoverthepowersupplyvoltagerange.Outputclockjitterismeasuredwithacycle-to-cyclejitterof+/−3nsappliedtotheinputclocksignalwhiledatainputsareswitching(SeeFigures15and16).Ajittereventof3ns,representsworsecasejumpintheclockedgefrommostgraphicscontrollerVGAchipscurrentlyavailable.ThisparameterisusedwhencalculatingsystemmarginasdescribedinAN-1059.

ACTimingDiagrams

10086804

FIGURE1.“WorstCase”TestPattern(Note7)

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DS90C385/DS90C365ACTimingDiagrams

(Continued)

10086805

FIGURE2.“16Grayscale”TestPattern-DS90C385(Notes8,9,10)

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DS90C385/DS90C365ACTimingDiagrams

(Continued)

10086831

FIGURE3.“16Grayscale”TestPattern-DS90C365(Notes8,9,10)

Note7:Theworstcasetestpatternproducesamaximumtogglingofdigitalcircuits,LVDSI/OandCMOS/TTLI/O.

Note8:The16grayscaletestpatterntestsdevicepowerconsumptionfora“typical”LCDdisplaypattern.Thetestpatternapproximatessignalswitchingneededtoproducegroupsof16verticalstripesacrossthedisplay.

Note9:Figures1,2showafallingedgedatastrobe(TxCLKIN/RxCLKOUT).

Note10:Recommendedpintosignalmapping.Customermaychoosetodefinedifferently.

10086830

FIGURE4.DS90C385/DS90C365(Transmitter)LVDSOutputLoad

10086806

FIGURE5.DS90C385/DS90C365(Transmitter)LVDSTransitionTimes

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DS90C385/DS90C365ACTimingDiagrams

(Continued)

10086808

FIGURE6.DS90C385/DS90C365(Transmitter)InputClockTransitionTime

10086810

FIGURE7.DS90C385/DS90C365(Transmitter)Setup/HoldandHigh/LowTimes(FallingEdgeStrobe)

10086812

FIGURE8.DS90C385/DS90C365(Transmitter)ClockIntoClockOutDelay

10086814

FIGURE9.DS90C385/DS90C365(Transmitter)PhaseLockLoopSetTime

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DS90C385/DS90C365ACTimingDiagrams

(Continued)

10086817

FIGURE10.28ParallelTTLDataInputsMappedtoLVDSOutputs-DS90C385

10086832

FIGURE11.21ParallelTTLDataInputsMappedtoLVDSOutputs-DS90C365

10086818

FIGURE12.TransmitterPowerDownDelay

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DS90C385/DS90C365ACTimingDiagrams

(Continued)

10086826

FIGURE13.TransmitterLVDSOutputPulsePositionMeasurement-DS90C385

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DS90C385/DS90C365ACTimingDiagrams

(Continued)

10086833

FIGURE14.TransmitterLVDSOutputPulsePositionMeasurement-DS90C365

10086827

FIGURE15.TJCCTestSetup-DS90C385Shown

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DS90C385/DS90C365ACTimingDiagrams

(Continued)

10086828

FIGURE16.TimingDiagramoftheInputcycle-to-cycleclockjitter

DS90C385MTD56(TSSOP)PackagePinDescription—FPDLinkTransmitter

PinNameTxINTxOUT+TxOUT−TxCLKINR_FBTxCLKOUT+TxCLKOUT−PWRDOWNVCCGNDPLLVCCPLLGNDLVDSVCCLVDSGND

I/OIOOIIOOIIIIIII

No.284411111341213

Description

TTLlevelinput.Thisincludes:8Red,8Green,8Blue,and4controllines—FPLINE,FPFRAMEandDRDY(alsoreferredtoasHSYNC,VSYNC,DataEnable).PositiveLVDSdifferentiaIdataoutput.NegativeLVDSdifferentialdataoutput.TTLIevelclockinput.PinnameTxCLKIN.Programmablestrobeselect(SeeTable1).PositiveLVDSdifferentialclockoutput.NegativeLVDSdifferentialclockoutput.

TTLlevelinput.Assertion(lowinput)TRI-STATEStheoutputs,ensuringlowcurrentatpowerdown.SeeApplicationsInformationsection.PowersupplypinsforTTLinputs.GroundpinsforTTLinputs.PowersupplypinforPLL.GroundpinsforPLL.

PowersupplypinforLVDSoutputs.GroundpinsforLVDSoutputs.

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DS90C385/DS90C365DS90C385SLCSLC64A(FBGA)PackagePinSummary—FPDLinkTransmitter

PinNameTxINTxOUT+TxOUT−TxCLKINR_FBTxCLKOUT+TxCLKOUT−PWRDOWNVCCGNDPLLVCCPLLGNDLVDSVCCLVDSGNDNC

I/OIOOIIOOIIIIIII

No.2844111113512246

TTLlevelinput.

PositiveLVDSdifferentialdataoutput.NegativeLVDSdifferentialdataoutput.

TTLIeveIclockinput.Therisingedgeactsasdatastrobe.PinnameTxCLKIN.Programmablestrobeselect.HIGH=risingedge,LOW=fallingedge.PositiveLVDSdifferentialclockoutput.NegativeLVDSdifferentialclockoutput.

TTLlevelinput.Assertion(lowinput)TRI-STATEStheoutputs,ensuringlowcurrentatpowerdown.SeeApplicationsInformationsection.PowersupplypinsforTTLinputs.GroundpinsforTTLinputs.PowersupplypinforPLL.GroundpinsforPLL.

PowersupplypinforLVDSoutputs.GroundpinsforLVDSoutputs.Pinsnotconnected.

Description

DS90C385SLCSLC64A(FBGA)PackagePinDescription—FPDLinkTransmitter

ByPin

PinA1A2A3A4A5A6A7A8B1B2B3B4B5B6B7B8C1C2C3C4C5C6C7C8D1D2D3

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ByPinType

TypeIOOPPOOOIIGGOOGI

PinD3E4E8G1G6B3B4B7D5C6D6D7G5C8B2B1D2C1D1

OOGPIIIG

12

PinNameTxIN27TxOUT0-TxOUT0+LVDSVCCLVDSVCCTxCLKOUT-TxCLKOUT+TxOUT3+TxIN1TxIN0LVDSGNDLVDSGNDTxOUT2-TxOUT3-LVDSGND

NCTxIN3NCNCTxOUT1-TxOUT2+PLLGNDPLLVCCTxCLKINTxIN4TxIN2GND

PinNameGNDGNDGNDGNDGNDLVDSGNDLVDSGNDLVDSGNDLVDSGNDPLLGNDPLLGNDPWRDOWN

R_FBTxCLKINTxIN0TxIN1TxIN2TxIN3TxIN4TxIN5TxIN6TxIN7TxIN8TxIN9TxIN10TxIN11TxIN12

TypeGGGGGGGGGGGIIIIIIIIIIIIIIII

F1E2E3G2H1G3H3F4

DS90C385/DS90C365DS90C385SLCSLC64A(FBGA)PackagePinDescription—FPDLinkTransmitter(Continued)

ByPin

D4D5D6D7D8E1E2E3E4E5E6E7E8F1F2F3F4F5F6F7F8G1G2G3G4G5G6G7G8H1H2H3H4H5H6H7H8

G:GroundI:InputO:OutputP:Power

NC:NoConnect

ByPinType

OGGIIPIIGIPIGI

G4H4H5E5F5H6H7H8G7F7G8E7F8D8A1A6

IIIIGIIIIGIIIPIIIIII

A7A2A3C4D4B5C5B6A8A4A5C7E1E6H2B8C2C3F2F3F6

TxIN13TxIN14TxIN15TxIN16TxIN17TxIN18TxIN19TxIN20TxIN21TxIN22TxIN23TxIN24TxIN25TxIN26TxIN27TxCLKOUT-TxCLKOUT+TxOUT0-TxOUT0+TxOUT1-TxOUT1+TxOUT2-TxOUT2+TxOUT3-TxOUT3+LVDSVCCLVDSVCCPLLVCCVCCVCCVCCNCNCNCNCNCNC

IIIIIIIIIIIIIIIOOOOOOOOOOPPPPPP

TxOUT1+LVDSGNDPLLGNDPWDDOWNTxIN26VCCTxIN6TxIN7GNDTxIN16VCCTxIN24GNDTxIN5NCNCTxIN12TxIN17NCTxIN22TxIN25GNDTxIN8TxIN10TxIN13R_FBGNDTxIN21TxIN23TxIN9VCCTxIN11TxIN14TxIN15TxIN18TxIN19TxIN20

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DS90C385/DS90C365DS90C365PinDescription—FPDLinkTransmitter

PinNameTxINTxOUT+TxOUT−TxCLKINR_FBTxCLKOUT+TxCLKOUT−PWRDOWNVCCGNDPLLVCCPLLGNDLVDSVCCLVDSGND

I/OIOOIIOOIIIIIII

No.213311111341213

Description

TTLlevelinput.Thisincludes:6Red,6Green,6Blue,and3controllines—FPLINE,FPFRAMEandDRDY(alsoreferredtoasHSYNC,VSYNC,DataEnable).PositiveLVDSdifferentialdataoutput.NegativeLVDSdifferentialdataoutput.TTLIevelclockinput.PinnameTxCLKIN.Programmablestrobeselect(SeeTable1).PositiveLVDSdifferentialclockoutput.NegativeLVDSdifferentialclockoutput.

TTLlevelinput.Assertion(lowinput)TRI-STATEStheoutputs,ensuringlowcurrentatpowerdown.SeeApplicationsInformationsection.PowersupplypinsforTTLinputs.GroundpinsforTTLinputs.PowersupplypinforPLL.GroundpinsforPLL.

PowersupplypinforLVDSoutputs.GroundpinsforLVDSoutputs.

TRANSMITTERINPUTPINS

TheTxINandcontrolinputpinsarecompatiblewithLVC-MOSandLVTTLlevels.Thesepinsarenot5VtolerantTRANSMITTERINPUTCLOCK

Thetransmitterinputclockmustalwaysbepresentwhenthedeviceisenabled(PWRDOWN=HIGH).Iftheclockisstopped,thePWRDOWNpinmustbeusedtodisablethePLL.ThePWRDOWNpinmustbeheldlowuntilaftertheinputclocksignalhasbeenreapplied.ThiswillensureaproperdeviceresetandPLLlocktooccur.

POWERSEQUENCINGANDPOWERDOWNMODE

OutputsofthetransmitterremaininTRI-STATEuntilthepowersupplyreaches2V.Clockanddataoutputswillbegintotoggle10msafterVCChasreached3VandthePower-downpinisabove1.5V.EitherdevicemaybeplacedintoapowerdownmodeatanytimebyassertingthePowerdownpin(activelow).Totalpowerdissipationforeachdevicewilldecreaseto5µW(typical).

Thetransmitterinputclockmaybeappliedpriortopoweringupandenablingthetransmitter.Thetransmitterinputclockmayalsobeappliedafterpowerup;however,theuseofthePWRDOWNpinisrequiredasdescribedintheTransmitterInputClocksection.Donotpowerupandenable(PWRDOWN=HIGH)thetransmitterwithoutavalidclocksignalappliedtotheTxCLKINpin.

TheFPDLinkchipsetisdesignedtoprotectitselffromaccidentallossofpowertoeitherthetransmitterorreceiver.Ifpowertothetransmitboardislost,thereceiverclocks(inputandoutput)stop.Thedataoutputs(RxOUT)retainthestatestheywereinwhentheclocksstopped.Whenthereceiverboardlosespower,thereceiverinputsareshortedtoVCCthroughaninternaldiode.Currentislimited(5mAperinput)bythefixedcurrentmodedrivers,thusavoidingthepotentialforlatchupwhenpoweringthedevice.

ApplicationsInformation

TheDS90C385/DS90C365arebackwardcompatiblewiththeDS90C383/DS90C363,DS90C383A/DS90C363AandtheTSSOPversionsareapin-for-pinreplacements.Thedevice(DS90C385/DS90C365)utilizesadifferentPLLarchi-tectureemployinganinternal7Xclockforenhancedpulsepositioncontrol.

Thisdevice(DS90C385/DS90C365)alsofeaturesreducedvariationoftheTCCDparameterwhichisimportantfordualpixelapplications.(SeeAN-1084)TCCDvariationhasbeenmeasuredtobelessthan500psat85MHzundernormaloperatingconditions.

ThisdevicemayalsobeusedasareplacementfortheDS90CF583/563(5V,65MHz)andDS90CF581/561(5V,40MHz)FPD-LinkTransmitterswithcertainconsiderations/modifications:

Change5Vpowersupplyto3.3V.ProvidethissupplytotheVCC,LVDSVCCandPLLVCCofthetransmitter.2.TheDS90C385/DS90C365transmitterinputandcontrol

inputsaccept3.3VLVTTL/LVCMOSlevels.Theyarenot5Vtolerant.

3.ToimplementafallingedgedevicefortheDS90C385/

DS90C365,theR_FBpinmaybetiedtogroundORleftunconnected(aninternalpull-downresistorbiasesthispinlow).BiasingthispintoVccimplementsarisingedgedevice.

TRANSMITTERCLOCKJITTERCYCLE-TO-CYCLE

Figures15and16illustratethetimingoftheinputclockrelativetotheinputdata.Theinputclock(TxCLKin)isinten-tionallyshiftedtotheleft−3nsand+3nstotherightwhendata(Txin0-27)ishigh.This3nsofcycle-to-cycleclockjitterisrepeatedataperiodof2µs,whichistheperiodoftheinputdata(1µshigh,1µslow).AtdifferentoperatingfrequenciestheNCycleischangedtomaintainthedesired3nscycle-to-cyclejitterat2µsperiod.1.

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DS90C385/DS90C365PinDiagramforTSSOPPackages

DS90C385MTD

DS90CF365MTD

10086824

10086823

TypicalApplication

10086803

TABLE1.ProgrammableTransmitter(DS90C385/DS90C365)

PinR_FBR_FB

ConditionR_FB=VCCR_FB=GNDorNC

StrobeStatusRisingedgestrobeFallingedgestrobe

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DS90C385/DS90C365PhysicalDimensions

inches(millimeters)unlessotherwisenoted

56-LeadMoldedThinShrinkSmallOutlinePackage,JEDEC

DimensionsinmillimetersonlyOrderNumberDS90C385MTDNSPackageNumberMTD56

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DS90C385/DS90C365PhysicalDimensions

inches(millimeters)unlessotherwisenoted(Continued)

48-LeadMoldedThinShrinkSmallOutlinePackage,JEDEC

DimensionsinmillimetersonlyOrderNumberDS90C365MTDNSPackageNumberMTD48

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DS90C385/DS90C365+3.3VProgrammableLVDSTransmitter24-BitFlatPanelDisplay(FPD)Link-85MHz,+3.3VProgrammableLVDSTransmitter18-BitFlatPanelDisplay(FPD)Link-85MHzPhysicalDimensions

inches(millimeters)unlessotherwisenoted(Continued)

64ball,0.8mmfinepitchballgridarray(FBGA)Package

Dimensionsshowinmillimetersonly

OrderNumberDS90C385SLCNSPackageNumberSLC64A

LIFESUPPORTPOLICY

NATIONAL’SPRODUCTSARENOTAUTHORIZEDFORUSEASCRITICALCOMPONENTSINLIFESUPPORTDEVICESORSYSTEMSWITHOUTTHEEXPRESSWRITTENAPPROVALOFTHEPRESIDENTANDGENERALCOUNSELOFNATIONALSEMICONDUCTORCORPORATION.Asusedherein:1.Lifesupportdevicesorsystemsaredevicesorsystemswhich,(a)areintendedforsurgicalimplantintothebody,or(b)supportorsustainlife,andwhosefailuretoperformwhenproperlyusedinaccordancewithinstructionsforuseprovidedinthelabeling,canbereasonablyexpectedtoresultinasignificantinjurytotheuser.

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DeutschTel:+49(0)6995086208EnglishTel:+44(0)8702402171FrançaisTel:+33(0)141918790

2.Acriticalcomponentisanycomponentofalifesupportdeviceorsystemwhosefailuretoperformcanbereasonablyexpectedtocausethefailureofthelifesupportdeviceorsystem,ortoaffectitssafetyoreffectiveness.

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Email:ap.support@nsc.com

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Tel:81-3-5639-7560Fax:81-3-5639-7507

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Nationaldoesnotassumeanyresponsibilityforuseofanycircuitrydescribed,nocircuitpatentlicensesareimpliedandNationalreservestherightatanytimewithoutnoticetochangesaidcircuitryandspecifications.This datasheet has been download from:

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