专利名称：DEVICE AND PROCESSING ARCHITECTURE
FOR INSTRUCTION MEMORY EFFICIENCY
发明人：John Edward VINCENT,Peter Man Kin
SINN,Benton WATSON
申请号：US15068058申请日：20160311
公开号：US20170060579A1公开日：20170302
专利附图：
摘要：Different processor architectures are described to evaluate and trackdependencies required by instructions. The processors may hold or queue instructions
that require output of other instructions until required data and resources are availablewhich may remove the requirement of NOPs in the instruction memory to resolvedependencies and pipeline hazards. The processor may divide instruction data intobundles for parallel execution and provide speculative execution. The processor mayinclude various components to implement an evaluation unit, execution unit andtermination unit.
申请人：HUAWEI TECHNOLOGIES CO., LTD.
地址：Shenzhen CN
国籍：CN
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