现在的FPGA基本上都提供了Block RAM供用户使用，所以在自己的工程怎么用VHDL来使用这些Block RAM就非常重要。当然，还是推荐使用开发商提供的软件来生成一个RAM模块，但是这样的RAM块不论移植性还是灵活性都降低了。所以这里采用VHDL来描述一个RAM,对于不同的综合工具和约束条件，综合出的结果可能有所不同，尽管这样，其移植性和灵活性还是要比使用工具生成的RAM块好。使用不同的综合工具，只要稍加修改就可以满足自己设计的要求。
下面的VHDL代码使用ISE的XST综合，综合结果使用了Block RAM，这是我们期望的。当然有时对于用到的容量很小的RAM，我们并不需要其使用Block RAM，那么只要稍微修改一下就可以综合成Distribute RAM。具体如何修改后面再做介绍。
-------------------------------------------------------------------------------- -- Engineer: skycanny
-- Module Name: ram - Behavioral -- Tool versions: ISE 7.1
-- Description: This module is designed to generate a RAM -------------------------------------------------------------------------------- library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ram is
generic(width: integer := 16; -- used to change the memory data's width depth: integer := 8); -- used to change the memery address' width during -- instantiation. port(
clk : in std_logic; --clock
addr : in std_logic_vector(depth - 1 downto 0); --address bus cs : in std_logic; --chip select oe : in std_logic; --output enable --high for write --low for read
data_i: in std_logic_vector(width - 1 downto 0); --write data bus data_o: out std_logic_vector(width - 1 downto 0) --read data bus ); end ram;
architecture Behavioral of ram is
type ram is array(2 ** depth - 1 downto 0) of std_logic_vector(width - 1 downto 0); signal ram1 : ram;
begin process(clk) begin
if(clk'event and clk = '1') then if(cs = '0') then if(oe = '0') then
data_o <= ram1(conv_integer(addr)); else
ram1(conv_integer(addr)) <= data_i; end if; end if; end if; end process; end Behavioral;
----------------------------------------------------------------------------------------------------
我们看一下综合报告:
========================================================================= * HDL Synthesis *
=========================================================================
Synthesizing Unit Related source file is \"G:/vhdl/ram/ram.vhd\". Found 256x16-bit single-port block RAM for signal inferred 1 RAM(s). Unit 可见确实综合成了Block RAM。并且只要改变Width和Depth，就可以改变生成RAM的宽度和容量 。 下面是把上面的代码稍做修改后生成Distribute RAM的代码和其综合报告，可见改动是非常小的。 entity ram is generic(width: integer := 16; -- used to change the memory data's width depth: integer := 8); -- used to change the memery address' width during -- instantiation. port( clk : in std_logic; --clock addr : in std_logic_vector(depth - 1 downto 0); --address bus cs : in std_logic; --chip select oe : in std_logic; --output enable --low for read wr : in std_logic; --low for write --add for distribute ram data_i: in std_logic_vector(width - 1 downto 0); --write data bus data_o: out std_logic_vector(width - 1 downto 0) --read data bus ); end ram; architecture Behavioral of ram is type ram is array(2 ** depth - 1 downto 0) of std_logic_vector(width - 1 downto 0); signal ram1 : ram; begin process(clk) begin if(clk'event and clk = '1') then if(cs = '0') then if(oe = '0') then data_o <= ram1(conv_integer(addr)); elsif(wr = '0') then --change for distribute ram ram1(conv_integer(addr)) <= data_i; end if; end if; end if; end process; end Behavioral; ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit Related source file is \"G:/vhdl/ram/ram.vhd\". Found 256x16-bit single-port distributed RAM for signal | ram_style | Auto | | ----------------------------------------------------------------------- Found 16-bit register for signal inferred 16 D-type flip-flop(s). Unit 由以上的讨论我们可以看出，用VHDL来描述RAM其实是非常方便，更加重要的这种方法在移植是时候有着更加优越的特点。 现在的FPGA基本上都提供了Block RAM供用户使用，所以在自己的工程怎么用VHDL来使用这些Block RAM就非常重要。当然，还是推荐使用开发商提供的软件来生成一个RAM模块，但是这样的RAM块不论移植性还是灵活性都降低了。所以这里采用VHDL来描述一个RAM,对于不同的综合工具和约束条件，综合出的结果可能有所不同，尽管这样，其移植性和灵活性还是要比使用工具生成的RAM块好。使用不同的综合工具，只要稍加修改就可以满足自己设计的要求。 下面的VHDL代码使用ISE的XST综合，综合结果使用了Block RAM，这是我们期望的。当然有时对于用到的容量很小的RAM，我们并不需要其使用Block RAM，那么只要稍微修改一下就可以综合成Distribute RAM。具体如何修改后面再做介绍。 -------------------------------------------------------------------------------- -- Engineer: skycanny -- Module Name: ram - Behavioral -- Tool versions: ISE 7.1 -- Description: This module is designed to generate a RAM -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity ram is generic(width: integer := 16; -- used to change the memory data's width depth: integer := 8); -- used to change the memery address' width during -- instantiation. port( clk : in std_logic; --clock addr : in std_logic_vector(depth - 1 downto 0); --address bus cs : in std_logic; --chip select oe : in std_logic; --output enable --high for write --low for read data_i: in std_logic_vector(width - 1 downto 0); --write data bus data_o: out std_logic_vector(width - 1 downto 0) --read data bus ); end ram; architecture Behavioral of ram is type ram is array(2 ** depth - 1 downto 0) of std_logic_vector(width - 1 downto 0); signal ram1 : ram; begin process(clk) begin if(clk'event and clk = '1') then if(cs = '0') then if(oe = '0') then data_o <= ram1(conv_integer(addr)); else ram1(conv_integer(addr)) <= data_i; end if; end if; end if; end process; end Behavioral; ---------------------------------------------------------------------------------------------------- 我们看一下综合报告: HDL Synthesis Synthesizing Unit Related source file is \"G:/vhdl/ram/ram.vhd\". Found 256x16-bit single-port block RAM for signal 可见确实综合成了Block RAM。并且只要改变Width和Depth，就可以改变生成RAM的宽度和容量 。 下面是把上面的代码稍做修改后生成Distribute RAM的代码和其综合报告，可见改动是非常小的。 entity ram is generic(width: integer := 16; -- used to change the memory data's width depth: integer := 8); -- used to change the memery address' width during -- instantiation. port( clk : in std_logic; --clock addr : in std_logic_vector(depth - 1 downto 0); --address bus cs : in std_logic; --chip select oe : in std_logic; --output enable --low for read wr : in std_logic; --low for write --add for distribute ram data_i: in std_logic_vector(width - 1 downto 0); --write data bus data_o: out std_logic_vector(width - 1 downto 0) --read data bus ); end ram; architecture Behavioral of ram is type ram is array(2 ** depth - 1 downto 0) of std_logic_vector(width - 1 downto 0); signal ram1 : ram; begin process(clk) begin if(clk'event and clk = '1') then if(cs = '0') then if(oe = '0') then data_o <= ram1(conv_integer(addr)); elsif(wr = '0') then --change for distribute ram ram1(conv_integer(addr)) <= data_i; end if; end if; end if; end process; end Behavioral; * HDL Synthesis * Synthesizing Unit Related source file is \"G:/vhdl/ram/ram.vhd\". Found 256x16-bit single-port distributed RAM for signal inferred 16 D-type flip-flop(s). Unit 由以上的讨论我们可以看出，用VHDL来描述RAM其实是非常方便，更加重要的这种方法在移植是时候有着更加优越的特点。 因篇幅问题不能全部显示，请点此查看更多更全内容